RRAM Device Optimization and Circuit Design for Low Power Low Latency Domain Specific Edge Applications

Abstract

Conventional von Neumann computing architecture has little parallelism and physically divides memory and logic units. In-memory computation offers further opportunity for power and efficiency improvements as data transport between memory and logic units introduces substantial power consumption and latency. RRAM memory devices are a non-volatile, highly scalable alternative that is compatible with advanced logic CMOS processes. Because of its in-memory computing capabilities, it is a more appealing solution for data-intensive applications. Depending on the needs of the application, RRAM's different switching types such as binary switching, multilayer switching, and analog switching can be employed. These devices can be utilized in applications where they must continuously update their condition (e.g neural network training). The RRAM memory system can be of great use in applications where the device must continuously maintain the resistance state as well, either with or without in-memory processing. Moreover, RRAM devices are currently being researched for in-sensor or near-sensor applications to speed up AI inference. The diversity of RRAM switching schemes and application range creates vast research opportunities to examine the viability of these devices. Hence, leveraging RRAM’s unique switching properties analog (continuous) or binary/multilevel switching, in-memory computation scheme (MAC or bit-wise) as well as integration location (in-pixel, near pixel or memory) there is still a wide range of different applications yet to be explored. In this work, RRAM analog switching properties of based on different materials stacks, inference-like applications such as error correcting code implementation, genome alignment, and in-sensor AI inference acceleration have been investigated.