Reliability and Performance Optimization of Resistive Random-Access Memory Devices for Advanced Computing and Memory Applications

Abstract

Current trends towards more efficient computing include alternatives to the standard von Neumann architecture and a trend towards in-memory computing with non-volatile memory (NVM) arrays. Resistive Random-Access Memory (ReRAM) is a strong NVM candidate for such applications. In this work, performance optimization and reliability studies were performed using hafnium oxide and tantalum oxide-based ReRAM devices integrated into 65nm CMOS. A thorough analysis of the effects of switching parameters such as maximum current, voltage, pulse width, and temperature-based stress culminated in improved device performance, yielding a memory window (MW) > 30, excellent endurance >2.1x1010, and retention at multiple resistance levels for 104 seconds without degradation. When the operational temperature was ramped from 25-125 °C oxygen vacancy mobility and generation rates shifted in these devices, directly affecting MW by up to 2X. To demonstrate the potential of ReRAM for neuromorphic applications, multilevel (analog) switching was implemented, achieving a total of >10 statistically distinct resistance levels when using large (>50 ns) pulses. When using ultra-short pulses (300 ps) the number of resistance states was limited to < 15 and resulted in a narrow conduction window (CW) of ~2X. Thus, an optimized pulsing scheme, incremental pulsing (ISPP), was utilized in which successive switching pulses increase in voltage amplitude. When used in conjunction with a read-verify scheme, the total number of resistance states increased to >20 and the CW increased to ~31X respectively, while also maintaining the linearity and symmetry of potentiation or depression. Based on these empirical data, the Neural Network (NN) learning algorithm “Cross-Sim” simulator was trained on the MNIST dataset, yielding 96.55% accuracy, on a 96.7% baseline, when using the ISPP algorithm. Taken together, these results demonstrate the potential of ReRAM 24 for non-von Neumann computing applications once proper optimization of electrical switching parameters and operational temperature is achieved.