Low power partial product reduction stage for booth multiplier

Abstract

In this thesis, we explore different avenues to reduce the power consumption of a 16x16 Multiplier. Our approach focuses on an interconnection pattern for the partial product reduction stage of the multiplier, which is divided into three stages. Each stage uses, half adder, full adder and 4:2 compressor modules in its design. The outputs from each stage connect to the inputs of the next stage. The interconnection pattern is based on an effective input capacitance, a parameter defined for each input lead of a logic device. Based on our strategy, the output with the highest switching activity at stage N is connected to the input with the lowest effective capacitance at stage N+1. This approach will result in minimizing the overall power dissipation of the entire partial product reduction stage for the 16x16 Multiplier. The design was carried out using 50nm CMOS technology using Electric VLSI tools, and simulations were carried out using LTspice. Our design was verified by simulation, and was found to consume 1.8mW of power. This is more than 10% less compared to the ones reported in literature.