Resist and Process Pattern Variations in Advanced Node Semiconductor Device Fabrication

Abstract

Pattern variations can cause challenges in device scaling. Since the last few decades, the semiconductor industry has successfully utilized the device scaling technique by reducing the transistor area to meet the requirements needed for optimum device performance and fabrication cost during each generation of development. The main challenges in the development of this technique are imaging resolution and pattern variations. Extreme ultraviolet (EUV) lithography and the multiple-patterning method can be used to push the imaging resolution to sub-30 nm. This thesis investigates the mechanism of pattern variations and proposes methods for pattern improvement. The thesis begins by investigating the origin of pattern variations in an EUV–chemically amplified photoresist system. The experimental results show that the chemical composition and inhomogeneity of the material contribute to pattern variations in EUV lithography. A difference in the localized-material-removal rate indicates the contribution of stochastics chemical kinetics in the photoresist during the development process. The study then investigates the effects of the plasma etching process on the pattern variations. The plasma etching process can alter the pattern variations by modifying the etching behavior and the etching selectivity. The thesis also discusses the system-level or integrated process-induced pattern variations. The method proposed herein involves surface modification and tone inversion technique and reduces the line edge roughness by 26% on a 20-nm pitch line pattern. Using a multicolor line-cut process, the thesis experimentally demonstrated the control of the edge-placement error from system-level pattern variations.