• Bypassing fingerprint scanners using artificial fingerprints

      Ford, Kerry C. (2021-05)
      Although fingerprint scanning technology is a convenient and user-friendly method of securing many modern devices, it is not without its flaws. In this paper, a methodology for creating artificial fingerprints is presented, as well as the experimental results, in order to display several low-cost techniques that can be used to bypass modern fingerprint sensors. Three methods are employed: direct collection, indirect collection (mold), and indirect collection (copy). First, using direct collection, a mold and cast of a physical fingerprint is created using very low-cost materials. Second, a fingerprint is indirectly collected from a surface and is used to create a 3D printed mold. Finally, a fingerprint is gathered using the indirect collection method, but is then inverted to achieve a higher resolution 3D printed copy of the original finger. Experimental results are presented, showing the effectiveness of the three fingerprint fabrication techniques on optical and capacitive sensors. Experimental results reveal that it is possible to bypass most sensors 80-100% of the time. The artificial fingerprints produced this way are reusable for many months. This was accomplished using widely available tools, and at a lower cost than that which has been previously reported in other research.
    • Low power partial product reduction stage for booth multiplier

      Jawharji, Mahmoud (2017-05)
      In this thesis, we explore different avenues to reduce the power consumption of a 16x16 Multiplier. Our approach focuses on an interconnection pattern for the partial product reduction stage of the multiplier, which is divided into three stages. Each stage uses, half adder, full adder and 4:2 compressor modules in its design. The outputs from each stage connect to the inputs of the next stage. The interconnection pattern is based on an effective input capacitance, a parameter defined for each input lead of a logic device. Based on our strategy, the output with the highest switching activity at stage N is connected to the input with the lowest effective capacitance at stage N+1. This approach will result in minimizing the overall power dissipation of the entire partial product reduction stage for the 16x16 Multiplier. The design was carried out using 50nm CMOS technology using Electric VLSI tools, and simulations were carried out using LTspice. Our design was verified by simulation, and was found to consume 1.8mW of power. This is more than 10% less compared to the ones reported in literature.