Holistic reliability study of BiCMOS emitter follower
dc.contributor.author | Caprotti, Nigel | |
dc.date.accessioned | 2024-05-20T16:46:46Z | |
dc.date.available | 2024-05-20T16:46:46Z | |
dc.date.issued | 2024-05 | |
dc.identifier.uri | http://hdl.handle.net/20.500.12648/14842 | |
dc.description.abstract | The interdisciplinary nature of semiconductors engineering is undeniable, as electrical, chemical, and mechanical disciplines are all heavily involved in the design of integrated chips. The many specialties of integrated circuit manufacturing and design include the processes involved in fabrication, device testing, feature size metrology, defect analysis, and the list goes on. One notable subfield is integrated circuit reliability, the study of the physical degradation mechanisms of chips like hot-carrier injection, electromigration, and time-dependent dielectric breakdown. The research and seminal progress in this important field have been a mélange of both empirical results as well as first principle theoretical realizations. This paper studies the reliability of a basic BiCMOS emitter voltage follower comprised of several passive elements, as well as two MOSFET transistors and an NPN bipolar junction transistor. The modeling and circuit design was enabled by the GlobalFoundries open-source 180 nm microcontroller process design kit. Employing Xschem and Ngspice for schematic-level simulation, and KLayout for layout generation and design rule verification, the performance and physical model of the circuit were established using only open-source software. Thermal finite element modeling using SolidWorks was undertaken to predict the temperature distribution of the circuit due to Joule heating. A holistic consideration of circuit reliability is offered, with special credence given to the electromigration of the first- and second-level metal interconnects. This paper will assess the degradation of individual circuit components (mean-time-to-failure), propose strategies to mitigate potential reliability risks, and posit a final layout using BiCMOS circuitry and the open-source process design kit. Author Keywords: Hot carrier injection, metal oxide semiconductors, field effect transistors, front-end-of-line degradation, back-end-of-line degradation, layout, electromigration, microelectronics reliability, BiCMOS | en_US |
dc.language.iso | en_US | en_US |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 International | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | Research Subject Categories::TECHNOLOGY::Electrical engineering, electronics and photonics::Electrical engineering | en_US |
dc.subject | Electrical engineering | en_US |
dc.subject | Metal oxide semiconductors | en_US |
dc.subject | Metal oxide semiconductors, Complementary -- Design and construction | en_US |
dc.title | Holistic reliability study of BiCMOS emitter follower | en_US |
dc.type | Masters Thesis | en_US |
dc.description.version | NA | en_US |
refterms.dateFOA | 2024-05-20T16:46:48Z | |
dc.description.institution | SUNY College at New Paltz | en_US |
dc.description.department | Electrical Engineering | en_US |
dc.description.degreelevel | MS | en_US |
dc.description.advisor | Wang, Ping-Chuan | |
dc.description.advisor | Liao, Jiun-Hsin | |
dc.description.advisor | Danesh, Wafi | |
dc.date.semester | Spring 2024 | en_US |
dc.accessibility.statement | If this SOAR repository item is not accessible to you (e.g. able to be used in the context of a disability), please email libraryaccessibility@newpaltz.edu | en_US |