Optimization of 1.2 kV 4H-Silicon Carbide (SiC) Power Devices: High Performance, Reliability, and Ruggedness

Abstract

This research primarily focuses on the design, fabrication, and characterization of 1.2 kV 4H-SiC devices. Power devices play a critical role in numerous high-power applications, including automotive, industrial and energy applications. The development of energy-efficient power devices is essential for reducing power loss during operation. While silicon-based power devices are widely used in high-power applications, they have reached their limit in minimizing power loss. As a result, wide-bandgap materials, particularly 4H-Silicon Carbide (SiC), have gained traction as replacements for their Silicon counterparts due to their superior material properties, enabling further reduction of power dissipation beyond Si. The demand for 1.2 kV 4H-SiC MOSFETs has significantly increased, particularly in the electric vehicle (EV) market where high performance, reliability, and ruggedness are critical to compete with Si counterparts. Hence, the optimization of 1.2 kV 4H-SiC devices is necessary. The most distinctive feature of a power device is its ability to withstand high voltages within the drift region. The breakdown voltage of the power device is determined by the specifications of the drift region. The optimization of the drift region must be performed to enhance power efficiency for each specific application due to the trade-off relationship between on-resistance and breakdown voltage. 4H-SiC enables a thin, heavily doped drift region to support a given breakdown voltage, resulting in a substantial reduction in the on-resistance of the device compared to Si. Moreover, Hybrid Junction Termination Extension (Hybrid-JTE) technique was employed to achieve a near-ideal breakdown voltage and experimentally verified.

The influence of deep JFET and P-well implants in 1.2 kV MOSFETs has been examined in terms of their impact on static characteristics and short-circuit ruggedness. To assess the impact on output characteristics and short-circuit ruggedness, the depths of JFET and P-well implants were compared by varying channel lengths and JFET widths. Furthermore, the significance of high channel mobility has been investigated not only for static characteristics but also for short-circuit characteristics.

The optimization of static characteristics of 1.2 kV 4H-SiC MOSFETs have been investigated through the analysis of the cell structure. A comprehensive analysis has been conducted to examine the trade-off relationship between specific on-resistance and breakdown voltage, as well as yield, by considering various dimensions within the cell structure. The dimensions explored in this analysis include the channel, JFET, contact opening, ILD (Inter-Layer Dielectric) width, and gate-to-source overlap within the cell structure.

A novel approach has been proposed to enhance the trade-off relationship between short-circuit withstand time and specific on-resistance by employing MOSFETs with a deep P-well structure through channeling implantation. For the channeling implantation, a tilt angle of 4 degrees was adjusted to <0001> direction of 4H-SiC in 4H-SiC (0001) substrates with 4 ° off-cut towered <11-20> direction. The utilization of channeling implantation has been employed to overcome the limitations associated with previous random implantation energy. The successful fabrication and demonstration of MOSFETs with deep P-well structures using channeling implantation have been achieved.

The MOSFETs with a deep P-well structure enable the short channel lengths, which improve the trade-off relationship between specific on-resistance and breakdown voltage. The implementation of a deep P-well structure effectively suppresses the leakage current originating from the channel during the blocking-mode of operation, thereby enhancing the trade-off relationship. Additionally, the deep P-well structure has significantly reduced the maximum electric field in the gate oxide, leading to improved high temperature reverse bias (HTRB) characteristics.

A novel layout approach has been proposed and successfully demonstrated for the monolithic integration of a Schottky diode with 1.2 kV SiC MOSFETs (JBSFETs) to achieve an identical cell pitch compared to the pure MOSFET design. To further reduce cell density, highly doped JFET implantation with narrow widths of JFET/Schottky regions has been conducted. Consequently, the proposed JBSFET demonstrates comparable static performance to the pure MOSFET while exhibiting 3rd quadrant current-voltage characteristics similar to JBS diodes.

A thorough comparison of the short-circuit failure mechanisms between 1.2 kV 4H-SiC MOSFETs and Ti JBSFETs, both having identical cell pitch and specific on-resistance, has been successfully accomplished. However, despite the same channel density, different short-circuit characteristics have been observed due to the presence of leakage current from the Schottky contact in the JBSFETs. In order to comprehend the short-circuit failure mechanisms, non-isothermal mixed-mode 2D TCAD device simulations have been employed. Moreover, based on the experimental results and analyses, potential solutions to further enhance the short-circuit characteristics of JBSFETs have been proposed.

A 1.2 kV 4H-SiC planar Junction Barrier Schottky (JBS) diode with a deep P+ grid structure, implemented through channeling implantation, has been successfully designed and fabricated. Without the use of a trench structure, a planar JBS diode with a junction depth of 2.2 μm has been successfully fabricated using an implantation energy of 350 keV. The formation of the deep junction significantly suppressed the leakage current originating from the Schottky contact.

In summary, extensive examinations have been conducted on 1.2 kV rated 4H-SiC power devices, including MOSFETs, JBSFETs, and JBS diodes, to optimize and enhance their static characteristics, dynamic characteristics, reliability, and ruggedness.