Development of 4H-SiC SMART (Scalable, Manufacturable, And Robust Technology) Power ICs

Abstract

The research primarily focuses on the design and development of SMART Power Integrated Circuits (ICs) in silicon carbide (4H-SiC). Over the past decades, power conversion has become more prevalent within the US as technological innovation has enabled the electrification of industrial systems, from energy to aerospace. Silicon (Si)-based power and CMOS devices have been the amicable semiconductor technology for power conversion. However, with the ever-evolving application space, the inherent material properties of Si hamper the capabilities in terms of power processing and high-temperature (HT) operation. The current generation power IC (multiple power integrated functions onto a single chip) technologies, predominantly Bulk-Silicon and Silicon-On-Insulator (SOI) technologies have limitations in their operational temperatures and power handling capability. Based on the theoretical limits, Si-based ICs are rated at 150 oC and are not operational beyond 200 oC due to leakage and reliability issues. Although SOI technology offers relief up to 300 oC, with the insulated region, it also fails beyond 300 oC. In recent decades, 4H-SiC has emerged as a reliable material for the development of high-voltage (HV) and high-temperature power devices. Due v to its superior material properties, 4H-SiC power devices can operate at high power and high temperatures when compared to their Si counterparts. In the current day scenario, Si-based power and control ICs drive the HV discrete 4H-SiC Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), and this technology appends to an increase in system footprint, and also in the parasitic effects from the interconnects hampering the reliability. Also, the high-temperature operation, one of the significant assets of 4H-SiC cannot be exploited. Hence, a single-chip 4H-SiC-based IC solution by monolithically integrating the HV Power MOSFET with low-voltage (LV) complementary metal-oxide-semiconductor (CMOS) can be a considerable solution to address the high power and extreme temperature challenges of the Si power ICs. The development of 4H-SiC-based power ICs is now seamlessly possible, thanks to considerable progress made over the last decade in material development and device fabrication. The exceptional advancements and the significant progress that was made in developing the technology platform for the demonstration of 4H-SiC Power ICs are reported in this dissertation. The fundamental step in designing the technology roadmap of a semiconductor material is understanding the trade-off performances of that particular semiconductor. Hence a detailed trade-off analysis was reported that was conducted on 4H-SiC and other wide bandgap semiconductors (GaN, Ga2O3, and diamond). This analysis concluded by letting the designers know the criticality of meticulous scrutiny and cautious selection of impact ionization coefficients from the existing literature to ensure accurate assessment and optimization of trade-off performance parameters. Additionally, simplified generalized equations for both non- vi punch-through (NPT) and punch-through (PT) design configurations to effectively design the drift layers in unipolar 4H-SiC power devices are documented. 2D-device, process simulations, and experimental demonstration of the HV lateral MOSFETs and diodes in 4H-SiC, specifically tailored for integration within power ICs are discussed. The cell designs, field management techniques, peripheral designs, and BV tailoring techniques of the HV lateral devices are reported in detail. The HV lateral devices are designed to operate at (400V-600V) and to be integrated with the Power ICs. The experimental results of the HV lateral devices demonstrate that the devices not only have the best-in-class Ron,sp - BV trade-off performance but are also capable of handling large currents validating efficient cell and peripheral design techniques. The design and analysis of critical module processes for CMOS development are also detailed. Channel engineering techniques (accumulation mode vs Inversion mode) are applied to match the threshold voltages (Vth) of the LV NMOS and PMOS. Multiple gate oxide recipes are developed to maximize the channel mobilities of electrons and holes. The results of the efforts dedicated to optimizing CMOS performance through improved ohmic contacts, including the investigation of metal contacts for simultaneous formation of n-type and p-type ohmic contacts were reported. The critical need for high-voltage isolation in power IC technology to ensure safety, reliability, and proper functioning was addressed. The utilization of junction isolation through the P+ Isolation junction implemented via Aluminum channeling implantation has been experimentally verified to yield promising blocking voltages required for the reliable operation vii of the ICs. Another HV isolation requirement which is the interlayer dielectric (ILD) voltage blocking between the adjacent metal layers carrying different voltage potentials is also addressed. Building upon the developed CMOS technology, the performance of digital CMOS ICs at extreme temperatures up to 400 °C has been demonstrated, covering packaging flow, assembly process, employed materials, and encountered challenges during HT measurements. This successful performance of the CMOS ICs at extreme temperatures (400 oC) further confirmed the potential of 4H-SiC as a promising material for the development of high-temperature electronics.