Browsing Colleges of Nanoscale Science and Engineering Doctoral Dissertations by Subject "von Neumann bottleneck"
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Application of Resistive Random Access Memory (RRAM) For Non-Von Neumann ComputingThe movement of data between physically separated memory and processing units in conventional computing systems (the so-called von Neumann architecture) incurs significant costs in energy and latency. This is known as the von Neumann bottleneck. With the advent of the Internet of Things (IoT) and edge computing, computing systems are also becoming significantly power limited. In this work, hafnium oxide resistive random access memory (ReRAM) integrated with 65nm CMOS technology on a 300 mm wafer platform was assessed to carry out two novel non-von Neumann computing applications that processes data within memory and avoid excessive data movement. These computing applications are based on regulating the flow of sneak path currents in memory arrays to perform computation, called flow-based computing, and detecting degree of association (correlation) between binary processes in an unsupervised manner using the ReRAM non-volatile accumulative behavior, termed as temporal correlation detection. Electrical characterization of hafnium oxide ReRAM arrays was conducted for multi-level resistance states for flow-based computing, which was then investigated for two functions, approximate edge detection and XOR Boolean logic, through both experiments and simulation. The effect of device non-idealities was also evaluated. A trade-off between the flow-based output resistance ratio and the variability of flow-based outputs was found for different patterned binary resistance Roff/Ron ratios. For the second non-von Neumann application, the feasibility of ReRAM as a non-volatile candidate device was investigated with an empirical ReRAM model through simulation. Experimental ReRAM analog incremental switching data, from both SET and RESET regimes, was also evaluated on the modified temporal correlation detection algorithm, where the RESET regime resulted in better performance. The ReRAM based implementation yielded 36,000-53,000 vi times lower energy consumption than similar implementation with phase change memory for 25 binary processes, and a speed-up of computation time by 1,600-2,100 times than that of a CPU-based implementation using 1xPOWER8 CPU. 1xPOWER8 CPU is a CPU available on the IBM* Power* System S822LC system, the POWER8 system series, where the CPU was run for 1 thread. In summary, hafnium oxide ReRAM based on 65nm CMOS technology has been evaluated for two non-von Neumann computing applications, and the effect of device non-idealities has also been assessed. These ReRAM in-memory computing applications show the promising potential of ReRAM in overcoming the von-Neumann bottleneck.